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AS5030 8-bit programmable high speed magnetic rotary encoder www.ams.com/AS5030 revision 2.4 1 - 44 1 general description the AS5030 is a contactless magnetic rotary encoder for accurate angular measurement over a full turn of 360. it is a system-on-chip, combining integrated hall elements, analog front end and digital signal processing in a single device. to measure the angle, only a simple two-pole magnet, rotating over the center of the chip is required. the absolute angle measurement provides instant indication of the magnet?s angular position with a resolution of 8 bit = 256 positions per revolution. this digital data is available as a serial bit stream and as a pwm signal. in addition to the angle information, the strength of the magnetic field is also available as a 6-bit code. data transmission can be configured for 1-wire (pwm), 2-wires (clk, dio) or 3-wires (clk, dio, cs). a software programmable (otp) zero position simplifies assembly as the zero position of the magnet does not need to be mechanically aligned. a power down mode together with fast startup- and measurement cycles allows for very low average power consumption and makes the AS5030 also suitable for battery operated equipment. figure 1. AS5030 block diagram 2 key features ?? 360 contactless angular position encoding ?? two digital 8-bit absolute outputs: - serial interface - pulse width modulated (pwm) output ?? user programmable zero position ?? direct measurement of magnetic field strength allows exact determination of vertical magnet distance ?? serial read-out of multiple interconnected AS5030 devices using daisy chain mode ?? wide magnetic field input range: 20 ~ 80mt ?? wide temperature range: -40c to +125c ?? small pb-free package: tssop 16 3 applications the AS5030 is suitable for contactless rotary position sensing, rotary switches (human machine interface), ac/dc motor position control, robotics and encoder for battery operated equipment. tracking adc & angle decoder hall array & front-end amplifier power management otp absolute serial interface (ssi) dio pwm clk prog cs pwm decoder cos sin agc dx c2 mag zero position agc angle magrngn sin / sinn / cos / cosn AS5030
www.ams.com/AS5030 revision 2.4 2 - 44 AS5030 datasheet - contents contents 1 general description ......................................................................................................... ......................................................... 1 2 key features................................................................................................................ ............................................................. 1 3 applications................................................................................................................ ............................................................... 1 4 pin assignments ............................................................................................................. .......................................................... 4 4.1 pin descriptions.......................................................................................................... .......................................................................... 4 5 absolute maximum ratings .................................................................................................... .................................................. 5 6 electrical characteristics.................................................................................................. ......................................................... 6 6.1 operating conditions...................................................................................................... ...................................................................... 6 6.2 system parameters ......................................................................................................... ..................................................................... 6 6.3 magnet specifications ..................................................................................................... ..................................................................... 7 6.4 magnetic field alarm limits ............................................................................................... .................................................................. 7 6.5 hall element sensitivity options.......................................................................................... ................................................................. 7 6.6 programming parameters .................................................................................................... ................................................................ 8 6.7 dc characteristics of digital inputs and outputs .......................................................................... ....................................................... 8 6.8 8-bit pwm output .......................................................................................................... ....................................................................... 9 6.9 serial 8-bit output....................................................................................................... .......................................................................... 9 6.10 general data transmission timings ........................................................................................ ........................................................ 10 7 detailed description........................................................................................................ ........................................................ 11 7.1 connecting the AS5030..................................................................................................... ................................................................. 11 7.2 serial 3-wire r/w connection.............................................................................................. .............................................................. 11 7.3 serial 3-wire read-only connection ........................................................................................ .......................................................... 13 7.4 serial 2-wire connection (r/w mode) ....................................................................................... ........................................................ 14 7.5 serial 2-wire continuous readout .......................................................................................... ........................................................... 15 7.6 serial 2-wire differential ssi connection................................................................................. .......................................................... 15 7.7 1-wire pwm connection ..................................................................................................... ........................................................... 16 7.8 analog output............................................................................................................. ........................................................................ 18 7.9 analog sin/cos outputs with external interpolator ......................................................................... ................................................... 19 7.10 3-wire daisy chain mode.................................................................................................. ............................................................... 20 7.11 2-wire daisy chain mode.................................................................................................. ............................................................... 21 8 application information ..................................................................................................... ...................................................... 22 8.1 AS5030 programming ........................................................................................................ ................................................................ 23 8.1.1 otp programming options ................................................................................................. ...................................................... 23 8.1.2 reduced power mode programming options .................................................................................. ......................................... 23 8.2 AS5030 read / write commands .............................................................................................. ........................................................ 23 8.2.1 16-bit read command..................................................................................................... .......................................................... 23 8.2.2 16-bit write command.................................................................................................... ........................................................... 24 8.2.3 18-bit otp read commands ............................................................................................... .................................................... 24 8.2.4 18-bit otp write commands .............................................................................................. ...................................................... 25 8.3 otp programming connection ................................................................................................ .......................................................... 26 8.3.1 programming in daisy chain mode ......................................................................................... .................................................. 26 8.4 programming verification .................................................................................................. ................................................................. 27
www.ams.com/AS5030 revision 2.4 3 - 44 AS5030 datasheet - contents 8.5 AS5030 status indicators .................................................................................................. ................................................................. 27 8.5.1 c2 status bit........................................................................................................... ................................................................... 27 8.5.2 lock status bit......................................................................................................... .................................................................. 27 8.5.3 magnetic field strength indicators ...................................................................................... ...................................................... 28 8.5.4 ?push-button? feature................................................................................................... ............................................................. 28 8.6 high speed operation ...................................................................................................... .................................................................. 29 8.6.1 propagation delay ....................................................................................................... .............................................................. 29 8.6.2 total propagation delay of the AS5030 .................................................................................. ................................................. 30 8.7 reduced power modes ....................................................................................................... ............................................................... 30 8.7.1 low power mode and ultra-low power mode................................................................................. ........................................... 31 8.7.2 power cycling mode...................................................................................................... ............................................................ 33 8.8 accuracy of the encoder system ............................................................................................ ........................................................... 34 8.8.1 quantization error...................................................................................................... ................................................................ 34 8.8.2 vertical distance of the magnet......................................................................................... ........................................................ 35 8.9 choosing the proper magnet................................................................................................ .............................................................. 36 8.9.1 magnet placement........................................................................................................ ............................................................. 37 8.9.2 lateral displacement of the magnet ...................................................................................... .................................................... 38 8.9.3 magnet size............................................................................................................. .................................................................. 39 8.10 physical placement of the magnet ......................................................................................... .......................................................... 40 9 package drawings and markings ............................................................................................... ............................................ 41 9.1 recommended pcb footprint................................................................................................. ........................................................... 42 10 ordering information....................................................................................................... ...................................................... 43
www.ams.com/AS5030 revision 2.4 4 - 44 AS5030 datasheet - pin assignments 4 pin assignments figure 2. pin assignments (top view) 4.1 pin descriptions table 1. pin descriptions pin number pin name pin type description 1 magrngn digital output / tri-state push-pull output. is ?high? when the magnetic field strength is too weak, e.g. due to missing magnet 2 prog supply pin programming voltage input. must be left open in normal operation. maximum load = 20pf (except during programming) 3 vss supply ground 4 t3_sinn - this pin is used for factory testing. for normal operation it must be left unconnected. inverse sin (sinn) output in sin/cos output mode 5 t2_sin - this pin is used for factory testing. for normal operation it must be left unconnected. sin output in sin/cos mode 6 t1_cosn - this pin is used for factory testing. for normal operation it must be left unconnected. inverse cos (cosn) output in sin/cos mode 7 t0_cos - this pin is used for factory testing. for normal operation it must be left unconnected. cos output in sin/cos mode 8 tc - test pin. connect to vss or leave unconnected 9 dx digital output digital output for 2-wire operation and daisy chain mode 10 clk digital input / schmitt-trigger clock input of synchronous serial interface; schmitt-trigger input 11 cs chip select for serial data transmission, active high; schmitt-trigger input, external pull-down resistor (~50k ) required in read-only mode 12 dio bi-directional digital pin data output / command input for digital serial interface 13 vdd supply pin positive supply voltage, 4.5v to 5.5v 14 c1 digital input (standard cmos; no pull-up or pull-down) configuration input: connect to vss for normal operation, connect to vdd to enable sin-cos outputs. this pin is scanned at power-on-reset and at wake-up from one of the ultra-low power modes 15 c2 configuration input: connect to vss for 3-wire operation, connect to vdd for 2-wire operation. this pin is scanned at power-on- reset and at wake-up from one of the ultra-low power modes 16 pwm digital output pulse width modulation output, 2s pulse width per step (2s ~ 512s) 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 prog vss test3 test2 test1 test0 tc magrngn dx clk cs dio vdd c1 c 2 pwm AS5030
www.ams.com/AS5030 revision 2.4 5 - 44 AS5030 datasheet - absolute maximum ratings 5 absolute maximum ratings stresses beyond those listed in table 2 may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in electrical characteristics on page 6 is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 2. absolute maximum ratings symbol parameter min max units comments electrical parameters v dd supply voltage -0.3 7 v except during otp programming v in input pin voltage vss - 0.5 vdd + 0.5 v i scr input current (latch-up immunity) -100 100 ma norm: jedec 78 electrostatic discharge esd electrostatic discharge 2 kv norm: mil 883 e method 3015 ja package thermal resistance 137 c/w still air / single layer pcb 89 c/w still air / multilayer pcb temperature ranges and storage conditions t strg storage temperature -55 +150 c min -67of; max +257of t body body temperature 260 c the reflow peak soldering temperature (body temperature) specified is in accordance with ipc/jedec j-std-020 ?moisture/reflow sensitivity classification for non-hermetic solid state surface mount devices?. the lead finish for pb-free leaded packages is matte tin (100% sn). humidity non-condensing 5 85 % msl moisture sensitive level 3 represents a maximum floor time of 168h
www.ams.com/AS5030 revision 2.4 6 - 44 AS5030 datasheet - electrical characteristics 6 electrical characteristics t amb = -40c to +125c, vdd5v = 4.5v ~ 5.5v, all voltages referenced to vss, unless otherwise noted. 6.1 operating conditions 6.2 system parameters symbol parameter conditions min typ max units v dd positive supply voltage 4.5 5.5 v i dd operating current no load on outputs. minimum agc (strong magnetic field) 14 18 ma no load on outputs. maximum agc (weak or no magnetic field) 18 22 i off power-down current low power mode 1400 2000 a ultra-low power mode 30 120 t amb ambient temperature -40f ~ +257f -40 125 c symbol parameter conditions min typ max units n resolution 8bit 1.406 t pwrup power up time startup from zero; agc not regulated 1000 s startup from zero until regulated agc 3300 startup from power down mode 500 startup from low power mode setting 1: no hysteresis, no reset 46 setting 2: hysteresis and reset 1500 t da propagation delay analog signal path; over full temperature range 15 17 s t dd tracking rate step rate of tracking adc; 1 step = 1.406 0.85 1.15 1.45 s t delay signal processing delay total signal processing delay, analog + digital (t da + t dd ) 16.15 18.45 s t analog filter time constant internal low-pass filter 4.1 6.6 12.5 s inl cm accuracy centered magnet -2 2 within horizontal displacement radius (see magnet specifications on page 7) -3 3 tn transition noise rms (1 sigma) 0.235 por r power-on-reset levels vdd rising 3.5 4.5 v por f vdd falling 3.0 4.5 v hyst hysteresis | por r - por f | 500 mv
www.ams.com/AS5030 revision 2.4 7 - 44 AS5030 datasheet - electrical characteristics 6.3 magnet specifications recommended magnet: ndfeb 35h br = 12.000 gauss, ?6mm x 2.5mm 6.4 magnetic field alarm limits 6.5 hall element sensitivity options symbol parameter conditions min typ max units md magnet diameter diametrically magnetized 6 mm mt magnet thickness 2.5 mm b i magnetic input range at chip surface, on a radius of 1mm 20 80 mt v i magnet rotation speed to maintain locked state 30.000 rpm b max magnetic field high detection t amb =25c, agc @ lower limit, 1 sigma = 2.5mt 52 mt b min magnetic field low detection t amb =25c, agc @ upper limit, 1 sigma = 1.5mt 23 hall array radius over x/y chip center 1 mm vertical distance of magnet recommended distance; operation outside this range is possible, accuracy may be reduced 0.5 1 1.8 mm horizontal magnet displacement radius from diagonal package center 0.25 mm from diagonal ic center 0.5 tk m recommended magnet material and temperature drift ndfeb material -0.12 %/k smco material -0.035 symbol parameter conditions min typ max units agc ff magnetic field too low alarm limit agc = ff h untrimmed, 25c, 1sigma 20.3 23.6 mt agc 0 magnetic field too high alarm limit agc = 0 h untrimmed, 25c, 1sigma 44.5 52.2 mt magnetic field alarm limit trim range (see hall element sensitivity options on page 7) 100 121 % temperature coefficient of alarm ranges sensitivity increases with temperature which partly compensates the temperature coefficient of the magnet 0.052 %/k symbol parameter conditions min typ max units sens hall element sensitivity setting sens = 00 (default); low sensitivity (see 18-bit otp write commands on page 25) 100 % sens = 01 106 sens = 10 113 sens = 11 (high sensitivity) 121
www.ams.com/AS5030 revision 2.4 8 - 44 AS5030 datasheet - electrical characteristics 6.6 programming parameters 6.7 dc characteristics of di gital inputs and outputs cmos inputs: clk, cs, dio, c1, c2 cmos outputs: dio, magrngn, pwm, dx cmos tristate output: dio symbol parameter conditions min typ max units v prog programming voltage static voltage at pin prog 8.0 8.5 v i prog programming current 100 ma tamb prog programming ambient temperature during programming 0 85 c t prog programming time timing is internally generated 2 4 s v r,prog analog readback voltage during analog readback mode at pin prog 0.5 v v r,unprog 2.2 3.5 symbol parameter conditions min typ max units v ih high level input voltage 0.7*vdd v v il low level input voltage 0.3*vdd v i leak input leakage current 1 a symbol parameter conditions min typ max units v oh high level output voltage source current <4ma vdd-0.5 v v oh low level output voltage sink current <4ma 0.4 v c l capacitive load 35 pf symbol parameter conditions min typ max units io z tristate leakage current cs = low 1 a
www.ams.com/AS5030 revision 2.4 9 - 44 AS5030 datasheet - electrical characteristics 6.8 8-bit pwm output 6.9 serial 8-bit output 3-wire interface. 2-wire interface. symbol parameter conditions min typ max units n pwm pwm resolution 8bit 2 s/step pw min pwm pulse width angle = 0 (00 h ) 1.66 2.26 2.85 s pw max pwm pulse width angle = 358.6 (ff h ) 427 578 731 s pw p pwm period over full temperature range 1 1. the tolerance of the absolute pwm pulse width and frequency can be eliminated by using the duty cycle t on /(t on +t off ) for angle measurement (see 1-wire pwm connection on page 16) . 428 581 734 s f pwm pwm frequency 1 / pwm period 1.72 khz hyst digital hysteresis 2 2. hysteresis may be temporarily disabled by software (see 16-bit write command on page 24) . at change of rotation direction 1 bit symbol parameter conditions min typ max units f clk clock frequency normal operation 6mhz t clk 166.6 ns f clk,p clock frequency during otp programming 250 500 khz symbol parameter conditions min typ max units f clk clock frequency normal operation 0.1 6 mhz t clk 166.6 10,000 ns f clk,p clock frequency during otp programming 250 500 khz t to synchronization timeout rising edge of clk to internally generated chip select on pin dx 16.6 27 34.3 ms hyst digital hysteresis 1 1. hysteresis may be temporarily disabled by software. at change of rotation direction 1 bit
www.ams.com/AS5030 revision 2.4 10 - 44 AS5030 datasheet - electrical characteristics 6.10 general data transmission timings see figure 5 for the corresponding timing diagram. symbol parameter conditions min typ max units t0 rising clk to cs clk/2 +0 clk/2 +50 ns t1 chip select to positive edge of clk 50 ns t2 chip select to drive bus externally 0 ns t3 setup time command bit data valid to positive edge of clk 50 ns t4 hold time command bit data valid after positive edge of clk 15 ns t5 float time positive edge of clk for last command bit to bus float clk/2 +0 ns t6 bus driving time positive edge of clk for last command bit to bus drive clk/2 +0 ns t7 setup time data bit data valid to positive edge of clk clk/2 +0 clk/2 +30 ns t8 hold time data bit data valid after positive edge of clk clk/2 +0 ns t9 hold time chip select positive edge clk to negative edge of chip select clk/2 +50 ns t10 bus floating time negative edge of chip select to float bus 50 ns t11 hold time data bit @ write access data valid to positive edge of clk 50 ns t12 hold time data bit @ write access data valid after positive edge of clk 15 ns t13 bus floating time negative edge of chip select to float bus 50 ns t to timeout period in 2-wire mode (from rising edge of clk) 20 24 s
www.ams.com/AS5030 revision 2.4 11 - 44 AS5030 datasheet - detailed description 7 detailed description the benefits of AS5030 are as follows: ?? complete system-on-chip, no calibration required ?? flexible system solution provides absolute serial and pwm output ?? ideal for applications in harsh environments due to magnetic sensing principle ?? high reliability due to non-contact sensing ?? robust system, tolerant to horizontal misalignment, airgap variations, temperature variations and external magnetic fields figure 3. typical arrangement of AS5030 and magnet 7.1 connecting the AS5030 the following examples show various ways to connect the AS5030 to an external controller: 7.2 serial 3-wire r/w connection in this mode, the AS5030 is connected to the external controller via three signals: chip select (cs), clock (clk) inputs and bi-directional dio (data in/out) output. the controller sends commands over the dio pin at the beginning of each data transmission sequence, such as reading the angle o r putting the AS5030 in and out of the reduced power modes. a pull-down resistor is not required. c1 and c2 are hardware configuration inputs . c1 must always be co nnected to vss, c2 selects 3-wire mode (c2 = low) or 2-wire mo de (c2 = high)
www.ams.com/AS5030 revision 2.4 12 - 44 AS5030 datasheet - detailed description figure 4. ssi read/write serial data transmission figure 5. timing diagram in 3-wire ssi r/w mode table 3. serial bit sequence (16-bit read/write) write command read / write data c4 c3 c2 c1 c0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 AS5030 micro controller 100 n cs clk dio +5 v vdd vss vss c 2 vdd vdd 13 11 10 12 15 c1 vss 3 14 i/o output output cmd 3 cmd 0 clk cs dio d15 t5 t3 t4 t6 t9 command phase data phase d14 d0 t10 dio dio write t1 dio read 123 4567 21 20 cmd4 d1 t7 t8 t clk
www.ams.com/AS5030 revision 2.4 13 - 44 AS5030 datasheet - detailed description 7.3 serial 3-wire read-only connection if the AS5030 is only used to provide the angular data (no power down or otp access) this simplified connection is possible. th e chip select (cs) and clock (clk) connection is the same as in the r/w mode, but only a digital input pin (not an i/o pin) is required for t he dio connection. as the first 5 bits of the data transmission are command bits sent to the AS5030, both the microcontroller and the AS5030 are c onfigured as digital inputs during this phase. therefore, a pull-down resistor must be added to make sure that the AS5030 reads ?00000? as t he first 5 bits which sets the read_angle command. all further application examples are shown in r/w mode, however read-only mode is also possible, unless otherwise noted. figure 6. ssi read-only serial data transmission figure 7. timing diagram in 2-wire and 3-wire ssi mode table 4. serial bit sequence (16-bit read/write) read d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 c2 lock agc angle d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 100 n cs clk dio +5 v vdd vss vss c 2 vdd vdd 13 11 10 12 15 c1 vss 3 14 input 10 k ... 100 k output output micro controller AS5030 clk cs dio d15 t9 command phase data phase t10 dio dio write t1 dio read 123 4567 21 8 d12 20 d14 d13 d0 d1
www.ams.com/AS5030 revision 2.4 14 - 44 AS5030 datasheet - detailed description 7.4 serial 2-wire connection (r/w mode) by connecting the configuration input c2 to vdd, the AS5030 is configured to 2-wire data transmission mode. only clock (clk) and data (dio) signals are required. a chip se lect (cs) signal is automatically generated by the dx output, wh en a time-out of clk occurs (typ. 20s). note: read-only mode is also possible in this configuration. figure 8. ssi r/w mode 2-wire data transmission figure 9. timing diagram in 2-wire ssi mode 100n cs clk dio +5 v vdd vss vss c2 vdd vdd 13 11 10 12 15 c1 vss 3 14 i/o output dx 9 AS5030 micro controller cmd4 clk cs dio read t0 t6 command phase data phase dio write t1 123 4567 22 dx 8 wait cycle (> 500 ns) cmd2 cmd3 cmd1 cmd0 d15 d14 d0 t5
www.ams.com/AS5030 revision 2.4 15 - 44 AS5030 datasheet - detailed description 7.5 serial 2-wire continuous readout the termination of each readout sequence by a timeout of clk after the 22 nd clock pulse as described in serial 2-wire connection (r/w mode) is the safest method to ensure synchronization, as each timeout of clk resets the serial interface. however, it is not mandatory to apply a timeout of clk and consequently synchronization after each reading. it is also possible to read several consecutive angle values without synchronization by simply continuing the clk pulses without timeout after the 22 nd clock. the 23 rd clock is equal to the 1 st clock of the next measurement, etc. this is the fastest way to read multiple angle values, as there is no timeout period between the readings. it is still possible to synchronize the serial data transmission by a timeout of clk after a given number of readouts (e.g. synchronize after every 5 th reading, etc.) figure 10. timing diagram in 2-wire ssi continuous readout 7.6 serial 2-wire differential ssi connection with the addition of a rs-422 / rs-485 transceiver, a fully differential data transmission, according to the 21-bit ssi interfa ce standard is possible. to be compatible with this standard, the clk signal must be inverted. this is done by reversing the data+ and data- l ines of the transceivers. note: this type of transmission is read-only. figure 11. 2-wire ssi read-only mode cmd4 clk cs dio read t0 t6 command phase data phase dio write t1 123 4567 22 dx 8 cmd2 cmd3 cmd 1 cmd 0 d15 d14 d0 t5 23 24 25 cmd 4 cmd2 cmd 3 1st reading 2nd reading command phase 100n cs clk dio +5 v vdd vss vss c2 vdd vdd 13 11 10 12 15 c1 vss 3 14 input output dx 9 clk di d+ d- d+ d- max 3081 or similar d+ d- d- d+ micro controller AS5030
www.ams.com/AS5030 revision 2.4 16 - 44 AS5030 datasheet - detailed description figure 12. timing diagram in 2-wire read only mode (differential transmission) 7.7 1-wire pwm connection this configuration uses the least number of wires: only one line (pwm) is used for data, leaving the total number of connection to three, including the supply lines. this type of configuration is especially useful for remote sensors. ultra-low power mode is not possible in this configuration, as there is no bi-directional data transmission. if the AS5030 angular data is invalid, the pwm output will remain at low state. pins that are not shown may be left open. note that the pwm output is invalid when the agc is disabled. figure 13. data transmission with pulse width modulated (pwm) output table 5. ssi read-only serial bit sequence (21bit read) read d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 c2 lock agc angle d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 123 45678 d14 d1 21 20 di clk d15 d0 t to timeout 100 n cs pwm +5 v vdd vss vss c 2 vdd vdd 13 11 16 15 c1 vss 3 14 input micro controller AS5030
www.ams.com/AS5030 revision 2.4 17 - 44 AS5030 datasheet - detailed description the minimum pwm pulse width t on (pwm = high) is 1 lsb @ 0 (angle reading = 00 h ). 1lsb = nom. 2.26s. the pwm pulse width increases with 1lsb per step. at the maximum angle 358.6 (angle reading = ff h ), the pulse width t on (pwm = high) is 256 lsb and the pause width t off (pwm = low) is 1 lsb. this leads to a total period (t on + t off ) of 257lsb. this means that the pwm pulse width is (position + 1) lsb, where position is 0?.255. the tolerance of the absolute pulse width and -frequency can be eliminated by calculating the angle with the duty cycle rather than with the absolute pulse width: (eq 1) results in an 8-bit value from 00 h to ff h , (eq 2) results in a degree value from 0 ~ 358.6 note: the absolute frequency tolerance is eliminated by dividing t on by (t on +t off ), as the change of the absolute timing effects both t on and t off in the same way. table 6. ssi read-only serial bit sequence (21-bit read) position angle high t_ high low t_ low duty-cycle 0 0 1 2.26s 256 578.56s 0.39% 127 178.59 128 287.02s 129 291.54s 49.4% 128 180 129 291.54s 128 287.02s 50.2% 255 358.59 256 578.56s 1 2.26s 99.6% 0 128 255 position 2. 26 s 291. 54 s 578. 56 s 2. 26 s 287. 02 s 578 . 56 s t on t off 0v 5v pwm out [] 1 257 8 ? ? ? ? ? ? ? ? ? + = ? off on on t t t bit angle [] ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + = 1 257 256 360 off on on t t t angle
www.ams.com/AS5030 revision 2.4 18 - 44 AS5030 datasheet - detailed description 7.8 analog output this configuration is similar to the pwm connection (only three lines including supply are required). with the addition of a lo w-pass filter at the pwm output, this configuration produces an analog voltage that is proportional to the angle. this filter can be either passive (as shown) or active. the lower the bandwidth of the filter, the less ripple of the analog ou tput can be achieved. if the AS5030 angular data is invalid, the pwm output will remain at low state and thus the analog output will be 0v. pins that are not shown may be left open. note: the pwm output is invalid when the agc is disabled. figure 14. data transmission with pulse width modulated (pwm) output figure 15. relation of pwm/analog output with angle 100n cs pwm +5 v vdd vss c2 vdd 13 11 16 15 c1 vss 3 14 >=4k7 >=4k7 >=1f >=1f analog out AS5030 0 180 360 angle 0v 5v pwmout analog out
www.ams.com/AS5030 revision 2.4 19 - 44 AS5030 datasheet - detailed description 7.9 analog sin/cos outputs wi th external interpolator by connecting c1 to vdd, the AS5030 provides analog sine and cosine outputs (sin, cos) of the hall array front-end for test pur poses. these outputs allow the user to perform the angle calculation by an external adc + c, e.g. to compute the angle with a high resoluti on. in addition, the inverted sine and cosine signals (sinn, cosn; see dotted lines) are available for differential signal transmis sion. the input resistance of the receiving amplifier or adc should be greater than 100k . the signal lines should be kept as short as possible, longer lines should be shielded in order to achieve best noise performance. the sin / cos / sinn / cosn signals are amplitude controlled to ~1 .3vp (differential) by the internal agc controller. the dc bi as voltage is 2.25v. if the sin(n)- and cos(n)- outputs cannot be sampled simultaneously, it is recommended to disable the automatic gain control as the signal amplitudes may be changing between two readings of the external adc. this may lead to less accurate results. figure 16. sine and cosine outputs for external angle calculation 100n sin cos +5 v vdd vss vss vss vdd vdd da d a sinn cosn c1 c2 14 13 3 15 5 4 7 6 micro controller AS5030
www.ams.com/AS5030 revision 2.4 20 - 44 AS5030 datasheet - detailed description 7.10 3-wire daisy chain mode the daisy chain mode allows connection of more than one AS5030 to the same controller interface. independent of the number of c onnected devices, the interface to the controller remains the same with only three signals: csn, clk and do. in daisy chain mode, the da ta from the second and subsequent devices is appended to the data of the first device. the 100nf buffer cap at the supply (shown only for the last device) is recommended for all devices. the total number of serial bits is: n*21, where n is the number of connected devices: e.g. for 2 devices, the serial bit stream is 42bits. for three devices it is 63 bits. figure 17. connection of devices in 3-wire daisy chain mode figure 18. timing diagram in 3-wire daisy chain mode #1 100n cs clk dio +5 v vdd vss vss c2 vdd vdd 13 11 10 12 15 c1 vss 3 14 i/o output output dx #2 cs clk dio c2 vdd 13 11 10 12 15 c1 vss 3 14 dx (last device) cs clk dio c2 vdd 13 11 10 12 15 c1 vss 3 14 dx AS5030 AS5030 AS5030 micro controller clk cs AS5030 # 1 cmd 3 dio 123 45678 cmd 1 cmd 2 cmd 0 d15 d14 d13 cmd 4 cmd 3 20 21 22 23 24 25 26 cmd 1 cmd 2 cmd 0 d 15 d14 d13 cmd 4 27 28 29 d0 cmd 3 41 42 43 44 cmd 2 cmd 4 d0 AS5030 # 2 AS5030 # 3
www.ams.com/AS5030 revision 2.4 21 - 44 AS5030 datasheet - detailed description 7.11 2-wire daisy chain mode the AS5030 can also be connected in 2-wire daisy chain mode, requiring only two signals (clock and data) for any given number o f daisy- chained devices. note that the connection of all devices except the last device is the same as for the 3-wire connection (see figure 17) . the last device must have pin c2 (#15) set to ?high? and feeds the dx signal to cs of the first device. again, each device should be buffered with a 100nf cap (shown only for the last device). the total number of serial bits is: n*21, where n is the number of connected devices. note that this configuration requires one extra clock (#1) to initiate the generation of the cs signal for the first device. after reading the last device, the communication must be reset b ack to the first device by introducing a timeout of clk (no rising edge for >24s) figure 19. 2-wire daisy chain mode figure 20. timing diagram in 2-wire daisy chain mode #1 100n cs clk dio +5 v vdd vss vss c 2 vdd vdd 13 11 10 12 15 c1 vss 3 14 i/o output dx #2 cs clk dio c2 vdd 13 11 10 12 15 c1 vss 3 14 dx (last device) cs clk dio c2 vdd 13 11 10 12 15 c1 vss 3 14 dx AS5030 micro controller AS5030 AS5030 clk cs (#1) as 5030 # 1 cmd 3 dio 123 45678 cmd 1 cmd 2 cmd 0 d15 d14 cmd 4 cmd 3 21 22 23 24 25 26 cmd 1 cmd 2 cmd 0 d 15 d14 cmd 4 27 28 29 d0 cmd 3 42 43 44 cmd 2 cmd 4 d0 AS5030 # 2 AS5030 # 3 cs (#2) cs (#3) 45
www.ams.com/AS5030 revision 2.4 22 - 44 AS5030 datasheet - application information 8 application information AS5030 parameter and features list. parameter description supply voltage 5v 10% supply current low power mode, non-operational: typ. 1.4ma ultra-low power mode, non-operational: typ. 30a normal operating mode: typ. 14ma. absolute output; serial interface 21-bit synchronous serial interface (ssi): 5 command bits, 2 data valid bits, 6 data bits for magnetic field strength, 8 data bits for angle. configurable for 2-wire (clock, data) or 3-wire (chip select, clock, data) operation daisy chain mode for reading multiple encoders through a 2- or 3-wire interface. zero position programming (otp) ssi clock rate 6 mhz data clock rate, 250 ~ 500khz during programming 2-wire readout mode dio and clk signals. 0.1 ~ 6mhz clock rate. synchronization through time-out of clk signal. power down modes activated and deactivated by software commands. low power mode: power down current = 1.4ma typ.; power up time <150s ultra-low power mode: power down current = 30a typ.; power up time <500s digital input cells clk, cs = schmitt trigger inputs sin-cos mode sine, inverse sine, cosine and inverse cosine outputs. 360 per period. maximum speed 30.000 rpm with locked adc resolution and accuracy resolution = 8-bit (1.406) accuracy 2 with centered magnet transition noise 0.24rms (1 sigma) pwm output 2.26s / step, pwm will be permanently low when angular data is not valid (e.g. during startup). digital output current 4ma @ vdd = 5v (pwm, dio, dx, magrngn outputs) otp programming mode through serial interface with static programming voltage on pin #2 (prog) 16-bit otp programming register. otp user programming options: angular zero position: 8 bit hall element sensitivity: 2 bit magnetic field range trimmable in four steps with otp programming (sensitivity) maximum/minimum ratio ~ 2.5:1. field range window = 20 ~ 80mt (e.g. maximum sensitivity range = 20 ~ 48mt, minimum sensitivity range = 32 ~ 80mt non-valid-range indication by hardware: magrngn pin indicates locked condition of adc by software: lock1&2 status bits indicate locked condition of adc start-up timings start-up time after shutdown < 2ms start-up time after power-down from ultra-low power mode: < 500s start-up time after power-down from low power mode: < 150s esd protection 2kv operating temperature -40c ~ +125c
www.ams.com/AS5030 revision 2.4 23 - 44 AS5030 datasheet - application information 8.1 AS5030 programming the AS5030 has an integrated 18-bit otp rom for configuration purposes. 8.1.1 otp programming options the otp programming options can be set permanently by programming or temporarily by overwriting. both methods are carried out o ver the serial interface, but with different commands (write otp, prog otp). note: during the 18bit otp programming, each bit needs 4 clock pulses to be validated. ?? zero position programming this programming option allows the user to program any rotation angle of the magnet as the new zero position. this useful featu re simpli- fies the assembly process as the magnet does not need to be mechanically adjusted to the electrical zero position. it can be as sembled in any rotation angle and later matched to the mechanical zero position by zero position programming. the 8-bit user programmable zero position can be applied both temporarily (command write otp, #1f h ) or permanently (command prog otp, #19 h ) ?? magnetic field optimization this programming option allows the user to match the vertical distance of the magnet with the optimum magnetic field range of t he AS5030 by setting the sensitivity level. the 2-bit user programmable sensitivity setting can be applied both temporarily (command write otp, #1f h ) or permanently (command prog otp, #19 h ) 8.1.2 reduced power mode programming options these temporary programming options are also carried out over the serial interface. ?? low power mode low power mode is a power saving mode with fast start-up. in low power mode, all internal digital registers are frozen and the power con- sumption is reduced to max. 1.5ma. the serial interface remains active. start-up from this mode to normal operation can be acco mplished within 150s. this mode is recommended for applications, where low power, but fast start-up and short reading cycle intervals a re required. ?? ultra-low power mode ultra-low power mode is a power saving mode with even reduced power-down current consumption. in this mode, all chip functions are fro- zen and the power consumption is reduced to max. 50a. the serial interface remains active. start-up from this mode to normal o peration can be accomplished within 500s. this mode is recommended for applications, where very low average power consumption is requir ed, e.g. for battery operated equipment. for example, in a cycled operation with 10 readings per second, the average power consumpt ion of the AS5030 can be reduced to only 120a. 8.2 AS5030 read / write commands data transmission with the AS5030 is handled over the 2-wire or 3-wire interface. the transmission protocol begins with sending a 5-bit command to the AS5030, followed by reading or writing 16 or 18 bits of data: 8.2.1 16-bit read command c2 displays status of hardware pin c2 (pin #15) lock indicates that the agc is locked. data is invalid when this bit is 0 agc 6-bit agc register. indicates the strength of the magnet (e.g. for push-button applications) 000000 b indicates a strong magnetic field 111111 b indicates a weak magnetic field ideally, the vertical distance of the magnet should be chosen such that the agc value is in the middle (around 100000b ) angle 8-bit angle value; represents the rotation angle of the magnet. one step = 360/256 = 1.4 command bin hex d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 rd angle 00000 00 c2 lock agc 5:0 angle 7:0
www.ams.com/AS5030 revision 2.4 24 - 44 AS5030 datasheet - application information 8.2.2 16-bit write command these settings are temporary; they cannot be programmed permanently. the settings will be lost when the power supply is removed . en prog command must be sent with a fixed 16-bit code (8cae h ) to enable subsequent otp access. ulp/lp n selects the ultra-low power mode, when bit psm is set: 0 = low power mode, 1 = ultra-low power mode psm enables power saving modes: 0 = normal operation, 1 = reduced power mode selected by bit ulp/lpn hys disables the hysteresis of the digital serial and pwm outputs: 0 (default) = 1-bit hysteresis, 1 = no hysteresis dis agc disables the automatic gain control. the agc will be frozen to a gain setting written in bits agc 5:0 (d6:d1), bit fa must be set. rst general reset: 0 = normal operation, 1 = perform general reset (required after return from reduced power modes) fa freeze agc; 0 = normal operation, 1= freeze agc with the values stored in bits agc 5:0. the pwm output will be invalid when bi t fa is set. 8.2.3 18-bit otp read commands note: to prohibit unintentional access to the otp register, otp prog/wri te access is only enabled after the en prog command has been sent. otp access is locked again by sending a rd angle or set pwr mode command. en prog need not to be sent before a read otp. during the 18bit otp read/write transfer, each bit needs 4 clock pulses to be validated. read otp reads the contents of the otp register in digital form. the reserved area may contain any value analog otp rd reads the contents of the otp register as an analog voltage at pin prog sens reads the sensitivity setting of the hall elements: 00 = low sensitivity, 11 = high sensitivity zero position reads the programmed zero position; the actual angle of the magnet which is displayed as 000 command bin hex d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 en prog1000010 1 0 00110010101110 set pwr mode 10001 11 ulp/ lpn psm 0 dis hyst 10011 13 hys 0 dis agc 10101 15 0 0 0 0 0 rst 0 0 0 agc 5:0 fa command bin hex d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 read otp 01111 0f reserved for factory settings sens 1:0 zero position 7:0 analog otp rd 01001 09 reserved for factory settings sens 1:0 zero position 7:0
www.ams.com/AS5030 revision 2.4 25 - 44 AS5030 datasheet - application information 8.2.4 18-bit otp write commands during the 18bit otp read/write transfer, each bit needs 4 clock pulses to be validated. write otp: non-permanent (?soft write?) modification of the otp register. to set the reserved factory settings area properly, a preceding read otp command must be made to receive the correct setting for bits d17:d10. the write otp command must then set these bits in exa ctly the same way. improper setting of the factory settings by a write otp command may cause malfunction of the chip. the otp register, including the factory settings can be restored to default by a power-up cycle. for non-permanent writing, a programming voltage at pin prog (#2) is not required. en_prog must be sent before write_otp to ena ble otp. prog otp: permanent modification of the otp register. an unprogrammed otp bit contains a ?0, programmed bits are 1?s. it is possible to program the otp in several sequences. however, only a 0 can be programmed to 1. once programmed, an otp bit cannot be set back to 0. for subsequent programming, bits that are already programmed should be set to 0 to avoid double programming. during permanent programming, the factory settings d17:d10 should always be set to zero to avoid modification of the factory se ttings. modifying the factory settings may cause irreversible malfunction of the chip. for permanent programming, a static programming voltage of 8.0-8.5v must be applied at pin prog (#2). en_prog must be sent bef ore prog_otp to enable otp. sens sets the sensitivity setting of the hall elements: 00: gain factor = 1.65 (low sensitivity) 01: gain factor = 1.75 10: gain factor = 1.86 11: gain factor = 2.00 (high sensitivity) zero position sets the user programmable zero position; the actual angle of the magnet which is displayed as 000 figure 21. timing diagram in otp 18-bit read/write mode command bin hex d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 write otp 11111 1f copy factory settings obtained from read otp command sens 1:0 zero position 7:0 prog otp 11001 19 00000000 reserved for factory settings, sens 1:0 zero position 7:0 hi hi cmd0 dclk cs dio t0 t2 t5 t3 t4 dio t6 command phase data phase extended d17 dio cmd2 d17 d16 d16 t7 t8 t11 t12 t10 read t13 write t1 t9 d0 d0
www.ams.com/AS5030 revision 2.4 26 - 44 AS5030 datasheet - application information 8.3 otp programming connection programming of the AS5030 otp memory does not require a dedicated programming hardware. the programming can be simply accomplis hed over the serial 3-wire interface (see figure 22) or the optional 2-wire interface (see figure 8) . for permanent programming (command prog otp, #19 h ), a constant dc voltage of 8.0v ~ 8.5v ( 100ma) must be connected to pin #2 (prog). for temporary otp write (?soft write?; command write otp, #1f h ), the programming voltage is not required. to secure unintentional programming, any modification of the otp memory is only enabled after a special password (command #10 h ) has been sent to the AS5030. figure 22. otp programming connection 8.3.1 programming in daisy chain mode programming in daisy chain mode is possible for both 3-wire and 2-wire mode (see figure 17 and figure 19 ). for temporary programming (soft write), no additional connections are required. programming is executed with the respective programming commands. for permanent programming, the programming voltage must be applied on pin#2 (prog) of the device to be programmed. it is also possible to app ly the programming voltage simultaneously to all devices, as the actual programming is only executed by a software command. a parallel connection of all prog-pins allows digital programming verification but does not allow analog programming verificati on. if analog programming verification is required, each prog pin must be selected individually for verification. 100 n cs clk dio +5 v vdd vss vss c 2 vdd vdd 13 11 10 12 15 c1 vss 3 14 i/o output output 8. 0 ? 8.5v prog 2 10f 100n micro controller AS5030
www.ams.com/AS5030 revision 2.4 27 - 44 AS5030 datasheet - application information 8.4 programming verification after programming, the programmed otp bits may be verified in two ways: - by digital verification: this is simply done by sending a read otp command (#0f h ). the structure of this register is the same as for the otp prog or otp write commands. - by analog verification: by sending an analog otp read command (#09 h ), pin prog becomes an output, sending an analog voltage with each clock, representing a sequence of the bits in the otp register. a voltage of <500mv indicates a correctly programmed bit (?1?) while a voltage leve l between 2.2v and 3.5v indicates a correctly unprogrammed bit (?0?). any voltage level in between indicates improper programming. figure 23. analog otp verification 8.5 AS5030 status indicators refer to 16-bit read command on page 23 . 8.5.1 c2 status bit this bit represents the hardware connection of the c2 configuration pin (#15) to determine, which hardware configuration is sel ected for the AS5030 in question. c2 = low: pin c2 is ?low?, indicating that the AS5030 is in 3-wire mode or a member of a 2-wire daisy chain connection (except the last) c2 = high: pin c2 is ?high?, indicating that the AS5030 is in 2-wire mode and/or the last member of a 2-wire daisy chain connec tion 8.5.2 lock status bit the lock signal indicates the adc lock status. if lock = low (adc unlocked), the angle information is invalid. to determine a valid angular signal at best performance, the following indicators should be set: lock = 1 agc > 00 h and < 2f h note: the angle signal may also be valid (lock = 1), when the agc is out of range (00 h or 2f h ), but the accuracy of the AS5030 may be reduced due to the out of range condition of the magnetic field strength. 100n cs clk dio +5 v vdd vss vss c 2 vdd vdd 13 11 10 12 15 c1 vss 3 14 i/o output output prog 2 v micro controller AS5030
www.ams.com/AS5030 revision 2.4 28 - 44 AS5030 datasheet - application information 8.5.3 magnetic field strength indicators the AS5030 is not only able to sense the angle of a rotating magnet, it can also measure the magnetic field strength (and hence the vertical distance) of the magnet. this extra feature can be used for several purposes: - as a safety feature by constantly monitoring the presence and proper vertical distance of the magnet - as a state-of-health indicator, e.g. for a power-up self test - as a push-button feature for rotate-and-push types of manual input devices the magnetic field strength information is available in two forms: magnetic field strength hardware indicator: pin magrngn (#1) will be ?high?, when the magnetic field is too weak. the switching limit is determined by the value of the agc. if the agc value is <3f h , the magrngn output will be ?low? (green range), if the agc is at its upper limit (3f h ), the magrngn output will be ?high? (red range). magnetic field strength software indicator: d13:d7 in the serial data that is obtained by command read angle contains the 6-bit agc information. the agc is an automatic gain control that adjusts the internal signal amplitude obtained from the hall element s to a constant level. if the magnetic field is weak, e.g. with a large vertical gap between magnet and ic, with a weak magnet or at elevated t emperatures of the magnet, the agc value will be ?high?. likewise, the agc value will be lower when the magnet is closer to the ic, when strong ma gnets are used and at low temperatures. the best performance of the AS5030 will be achieved when operat ing within the agc range. it will still be operational outside t he agc range, but with reduced performance especially with a weak magnetic field due to increased noise. factors influencing the agc value. in practical use, the agc value will depend on several factors: ?? the initial strength of the magnet. aging magnets may show a reducing magnetic field over time which results in an increase of the agc value. the effect of this phenomenon is relatively small and can easily be compensated by the agc. ?? the vertical distance of the magnet. depending on the mechanical setup and assembly tolerances, there will always be some varia tion of the vertical distance between magnet and ic over the lifetime of the application using the AS5030. again, vertical distance var iations can be compensated by the agc ?? the temperature and material of the magnet. the recommended magnet for the AS5030 is a diametrically magnetized, 5-6mm diameter ndfeb (neodymium-iron-boron) magnet. other magnets may also be used as long as they can maintain to operate the AS5030 within t he agc range. every magnet has a temperature dependence of the magnetic field strength. the temperature coefficient of a magnet depends on th e used material. at elevated temperatures, the magnetic field strength of a magnet is reduced, resulting in an increase of the agc val ue. at low temperatures, the magnetic field strength is increased, resulting in a decrease of the agc value. the variation of magnetic field strength over temperature is automatically compensated by the agc. otp sensitivity adjustment. to obtain best performance and tolerance against temperature or vertical distance fluctuations, the agc value at normal operating temperature should be in the middle between minimum and maximum, hence it should be around 100000 (20 h ). to facilitate the ?vertical centering? of the magnet+ic assembly, the sensitivity of the AS5030 can be adjusted in the otp regi ster in 4 steps. a sensitivity adjustment is recommended, when the agc value at normal operation is close to its lower limit (around 00 h ). the default sensitivity setting is 00 h = low sensitivity. 8.5.4 ?push-button? feature using the magnetic field strength software and hardware indicators described above, the AS5030 provides a useful method of dete cting both rotation and vertical distance simultaneously. this is especially useful in applications implementing a rotate-and-push type of human interface (e.g. in panel knobs and switches). the magrngn output is ?high?, when the magnetic field is below the low limit (weak or no magnet) and low when the magnetic fiel d is above the low limit (in-range or strong magnet). a finer detection of a vertical distance change, for example when only short vertical strokes are made by the push-button, is a chieved by memorizing the agc value in normal operation and triggering on a change from that nominal the agc value to detect a vertical mo vement.
www.ams.com/AS5030 revision 2.4 29 - 44 AS5030 datasheet - application information figure 24. magnetic field strength indicator 8.6 high speed operation the AS5030 is using a fast tracking adc (tadc) to determine the angle of the magnet. the tadc has a tracking rate of 1.15s (ty p). once the tadc is synchronized with the angle, it sets the lock bit in the status register. in worst case, usually at start-up, the tadc requires a maximum of 127 steps (127 * 1.15s = 146.05s) to lock. once it is locked, it requires only one cycle (1.15s) to track the mov ing magnet. the AS5030 can operate in locked mode at rotational speeds up to 30.000 rpm. in low power mode or ultra-low power mode, the position of the ta dc is frozen. it will continue from the frozen position once i t is powered up again. if the magnet has moved during the power down phase, several cycles will be required before the tadc is locked again. th e tracking time to lock in with the new magnet angle can be roughly calculated as: (eq 3) where: t lock = time required to acquire the new angle after power up from one of the reduced power modes [s] oldpos = angle position when one of the reduced power modes is activated [] newpos = angle position after resuming from reduced power mode [] 8.6.1 propagation delay the propagation delay is the time required from reading the magnetic field by the hall sensors to calculating the angle and mak ing it available on the serial or pwm interface. while the propagation delay is usually negligible on low speeds it is an important parameter at hi gh speeds. the longer the propagation delay, the larger becomes the angle error for a rotating magnet as the magnet is moving while the an gle is calculated. the position error increases linearly with speed. the main factors contributing to the propagation delay are: adc sampling rate. for high speed applications, fast adcs are essential. the adc sampling rate directly influences the propagation delay. the fast tracking adc used in the AS5030 with a tracking rate of only 1.15s (typ.) is a perfect fit for both high speed and hi gh performance. 100n cs clk dio +5 v vdd vss vss c 2 vdd vdd 13 11 10 12 15 c1 vss 3 14 i/o output output magrngn 1 led 1 1k micro controller AS5030 oldpos newpos s t lock ? ? = 15 . 1
www.ams.com/AS5030 revision 2.4 30 - 44 AS5030 datasheet - application information chip internal low-pass filtering. a commonplace practice for systems using analog-to-digital converters is to filter the input signal by an anti-aliasing filter. the filter characteristic must be chosen carefully to balance propagation delay and noise. the low-pass filter in the AS5030 has a cut-off frequency of typ. 23.8khz and the overall propagation delay in the analog signa l path is typ. 15.6s. digital readout rate. aside from the chip-internal propagation delay, the time required to read and process the angle data must also be considered. due to its nature, a pwm signal is not very usable at high speeds, as you get only one reading per pwm period. incr easing the pwm frequency may improve the situation but causes problems for the receiving controller to resolve the pwm steps. the frequenc y on the AS5030 pwm output is typ. 1.95khz with a resolution of 2s/step. a more suitable approach for high speed absolute angle measurement is using the serial interface. with a clock rate of up to 6m hz, a complete set of data (21bits) can be read in >3.5s 8.6.2 total propagation delay of the AS5030 the total propagation delay of the AS5030 is the delay in the analog signal path and the tracking rate of the adc: 15.6s + 1.15s = 16.75s. if only the sin-/cos-outputs are used, the propagation delay is the analog signal path delay only (typ. 15.6s). position error over speed. the angle error over speed caused by the propagation delay is calculated as: ? pd = rpm * 6 * 16.75e -6 in degrees (eq 4) in addition, the anti-aliasing filter causes an angle error calculated as: ? lpf = arctan [ rpm / ( 60*f 0 ) ] (eq 5) examples of the overall position error caused by speed, including both propagation delay and filter delay: 8.7 reduced power modes the AS5030 can be operated in 3 reduced power modes. all 3 modes have in common that they switch off or freeze parts of the chi p during intervals between measurements. in low power mode or ultra-low power mode, the AS5030 is not operational, but due to the fast s tart-up, an angle measurement can be accomplished very quickly and the chip can be switched to reduced power immediately after a valid meas urement has been taken. depending on the intervals between measurements, very low average power consumption can be achieved using such a strobed measurement mode. ?? low power mode:reduced current consumption, very fast start-up. ideal for short sampling intervals (<3ms) ?? ultra-low power mode:further reduced current consumption, but slower start-up than low power mode. ideal for sampling interva ls from 3?.200ms ?? power cycle mode:zero power consumption (externally switched off) during sampling intervals, but slower start-up than ultra-low power mode. ideal for sampling intervals 200ms speed (rpm) total position error ( ? pd + ? l pf ) 100 0.0175 1000 0.175 10000 1.75
www.ams.com/AS5030 revision 2.4 31 - 44 AS5030 datasheet - application information 8.7.1 low power mode and ultra-low power mode figure 25. low power mode and ultra-low power mode connection the AS5030 can be put in low power mode or ultra-low power mode by simple serial commands, using the regular connection for 2-w ire or 3- wire serial data transmission (see figure 4 and figure 8 ). the required serial command is set pwr mode (11 h ): note: after returning from low power mode or ultra-low power mode to normal operation (psm = 0), if the hysteresis is enabled (hys=0) , a general reset must be performed: set bit rst and then clear bit rst using command 15 h . the two following cases describe the typical loop programmed in the software: hys = 0. (1 lsb hysteresis) 1. wait for cpu interrupt or delay for next angle read (typ. <3ms in lp mode, typ>3ms in ulp mode) 2. wake up (psm = 0) 3. set reset (rst = 1) 4. clear reset (rst = 0) 5. wait 1.5ms (low power mode) 6. check if lock = 1 then read angle 7. enable low power mode or ultra-low power mode (psm=1) 8. return to 1 ulp / lpn psm mode 0 0 normal operation 0 1 low power mode 1 0 normal operation 1 1 ultra-low power mode AS5030 micro controller 100n cs clk dio +5v vdd vss vss vss vdd vdd on/off s n t on t off i on i off c1 c2 r1: optional; see text c1: optional; see text
www.ams.com/AS5030 revision 2.4 32 - 44 AS5030 datasheet - application information hys = 1. (no hysteresis) 1. wait for cpu interrupt or delay for next angle read (typ. <3ms in lp mode, typ>3ms in ulp mode) 2. wake up (psm = 0) 3. wait 0.01ms (low power mode) 4. check if lock = 1 then read angle 5. enable low power mode or ultra-low power mode (psm=1) 6. return to 1 the difference between low power mode and ultra-low power mode is the current consumption and the wake-up time to switch back t o active operation. in both reduced power modes, the AS5030 is inactive. the last state, e.g. the angle, agc value, etc. is frozen and the chip sta rts from this frozen state when it resumes active operation. this method provid es much faster start-up than a ?cold start? from zero. if the AS5030 is cycled between active and reduced current mode, a substantial reduction of the average supply current can be achieved. the minimum dwe lling time in active mode is the wake-up time. the actual active time depends on how much the magnet has moved while the AS5030 was in reduce d power mode. the angle data is valid, when the status bit lock has been set. once a valid angle has been measured, the AS5030 can be p ut back to reduced power mode. the average power consumption can be calculated as: (eq 6) sampling interval = t on + t off where: i avg average current consumption i active : current consumption in active mode i power_down :current consumption in reduced power mode t on :time period during which the chip is operated in active mode t off : time period during which the chip is in reduced power mode example: ultra-low power mode; sampling period = one measurement every 10ms. system constants = i active = 14ma, i power_down = 30a, ton(min) = 500s (startup from ultra-low power mode): (eq 7) see figure 27 for an overview table of the average current consumption in the various reduced power modes. reducing power supply peak currents. an optional rc-filter (r1/c1) may be added to avoid peak currents in the power supply line when the AS5030 is toggled between a ctive and reduced power mode. r1 must be chosen such that it can maintain a vdd voltage of 4.5v ~ 5.5v under all conditions, especially d uring long active periods when the charge on c1 has expired. c1 should be chosen such that it can support peak currents during the active operation period. for long active periods, c1 should be large and r1 should be small. mode current consumption (typ.) wake-up time to active operation active operation 14 ma 1.0 ms (without agc) 3.8 ms (with locked agc) low power mode 1.4 ma 0.15 ms ultra-low power mode 30 a 0.5 ms off on off down power on active avg t t t i t i i + ? + ? = _ a ms s ms a s ma i avg 729 5 , 9 500 5 , 9 * 30 500 14 = + + ? =
www.ams.com/AS5030 revision 2.4 33 - 44 AS5030 datasheet - application information 8.7.2 power cycling mode the power cycling method shown in figure 26 cycles the AS5030 by switching it on and off, using an external pnp transistor high side switch. this mode provides the least power consumption of all three modes; when the sampling interval is more than 400ms, as the curren t consumption in off-mode is zero. it also has the longest start-up time of all modes, as the chip must always perform a ?cold start? from zero, which takes about 1.9 ms. the optional filter r1/c1 may again be added to reduce peak currents in the 5v power supply line. figure 26. application example iii: ultra-low power encoder figure 26 shows an overview of the average supply currents in the thre e reduced power modes, depending on the sampling interval. the gra phs shows that the low power mode is the best option for sampling intervals <4ms, while the ultra-low power mode is the best option for sampling intervals between 4~400ms. at sampling intervals > 400ms, the power cycling mode is the best method to minimize the average cur rent consumption. the curves are based on the figures given in low power mode and ultra-low power mode on page 31 . figure 27. average current consumption of reduced power modes micro controller +5v vdd vss vss vdd 10k on/off c1 >1f r1 ton toff AS5030 100n cs clk dio vss vdd s n c1 c2 t on t off i on 0 AS5030 average current consumption 0,0 0,5 1,0 1,5 2,0 2,5 3,0 3,5 4,0 4,5 5,0 1 10 100 1000 samp ling interval [m s] avg. current consumption [m a low power mode power cycling mode ultra low power mode
www.ams.com/AS5030 revision 2.4 34 - 44 AS5030 datasheet - application information 8.8 accuracy of the encoder system this chapter describes which individual factors influence the accuracy of the encoder system and how to improve them. accuracy is defined as the difference between measured angle and actual angle. this is not to be confused with resolution, whic h is the smallest step that the system can resolve. the two parameters are not necessarily linked together. a high resolution encoder may not necessarily be highly accurate as wel l. 8.8.1 quantization error there is however a direct link between resolution and accuracy, which is the quantization error: figure 28. quantization error of a low resolution and a high resolution system the resolution of the encoder determines the smallest step size. the angle error caused by quantization cannot get better than ? lsb. as shown in figure 28 , a higher resolution system (right picture) has a smaller quantization error, as the step size is smaller. for the AS5030, the quantization error is ? lsb = 0.7 figure 29. typical inl error over 360 +? lsb -? lsb ideal function digitized function low resolution ideal function digitized function +? lsb -? lsb error high resolution quantization error inl including quantization error -1,5 -1 -0,5 0 0,5 1 1,5 0 45 90 135 180 225 270 315 360 angle steps inl [] inl average (16x)
www.ams.com/AS5030 revision 2.4 35 - 44 AS5030 datasheet - application information figure 29 shows a typical example of an error curve over a full turn of 360 at a given x-y displacement. the curve includes the quantiz ation error, transition noise and the system error. the total error is ~2.2 peak/peak ( 1.1). the sawtooth-like quantization error (see also figure 28 ) can be reduced by averaging, provided that the magnet is in constant motion and there are an adequate number of samples available. the solid bold line in figure 29 shows the moving average of 16 samples. the inl (intrinsic non- linearity) is reduced to from ~ 1.1 down to ~ 0.3. the averaging however, also increases the total propagation delay, there fore it may be considered for low speeds only or adaptive; depending on speed (see position error over speed on page 30) . 8.8.2 vertical distance of the magnet the chip-internal automatic gain control (agc) regulates the input signal amplitude for the tracking-adc to a constant value. t his improves the accuracy of the encoder and enhances the tolerance for the vertical distance of the magnet. figure 30. typical curves for vertical distance versus acg value on several untrimmed samples as shown in figure 30 , the agc value (left y-axis) increases with vertical distance of the magnet. consequently, it is a good indicator for determining the vertical position of the magnet, for example as a push-button feature, as an indicator for a defective magnet or as a preventive warning (e.g. for wear on a ball bearing etc.) when the nominal agc value drifts away. if the magnet is too close or the magnetic field is too strong, the agc will be reading 0, if the magnet is too far away (or missing) or if the magnetic field is too weak, the agc will be reading 63 (3f h ). the AS5030 will still operate outside the agc range, but the accuracy may be reduced as the signal amplitude can no longer be k ept at a constant level. the linearity curve in figure 30 (right y-axis) shows that the accuracy of theAS5030 is best within the agc range, even slightly better at small airgaps (0.4mm ~ 0.8mm). at very short distances (0mm ~ 0.1mm) the accuracy is reduced, mainly due to nonlinearities in the magnetic field. at larger distances, outside the agc range (~2.0mm ~ 2.5mm and mo re) the accuracy is still very good, only slightly decreased f rom the nominal accuracy. since the field strength of a magnet changes with temperature, t he agc will also change when the temperature of the magnet chan ges. at low temperatures, the magnetic field will be stronger and the agc valu e will decrease. at elevated temperatures, the magnetic field will be weaker and the agc value will increase. linearity and agc vs airgap 0 8 16 24 32 40 48 56 64 0 500 1000 1500 2000 2500 airgap [mm] agc value 1,0 1,2 1,4 1,6 1,8 2,0 2,2 linearity [] sample#1 sample#2 sample#3 sample#4 linearity [] [m]
www.ams.com/AS5030 revision 2.4 36 - 44 AS5030 datasheet - application information sensitivity trimming. as the curves for the 4 samples in figure 30 show, the agc value will not show exactly the same value at a given airgap on each part. for example, at 1mm vertical distance, the agc may read a value between ~11 ~ 24. this is because for norm al operation an exact trimming is not required since the agc is part of a closed loop system. however, the AS5030 offers an optional user trimming in the otp to allow an even tighter agc tolerance for applications where the information about magnetic field strength is also utilized, e.g. for rotate-and-push types of knobs, etc. 8.9 choosing the proper magnet figure 31. vertical magnetic fields of a rotating magnet note: there is no strict requirement on the type or shape of the magnet to be used with the AS5030. it can be cylindrical as well as square in shape. the key parameter is that the vertical magnetic field b z , measured at a radius of 1mm from the rotation axis is sinusoidal with a peak amplitude of 20 ~ 80mt. n s magnet axis vertical field component (20?80mt) 0 360 bz vertical field component r1 concentric circle; radius 1.0 mm r1 magnet axis typ. 6mm diameter s n
www.ams.com/AS5030 revision 2.4 37 - 44 AS5030 datasheet - application information 8.9.1 magnet placement ideally, the center of the magnet, the diagonal center of the ic and the rotation axis of the magnet should be in one vertical line. the lateral displacement of the magnet should be within 0.25mm from the ic package center or 0.5mm from the ic center, including the placement of the chip within the ic package. the vertical distance should be chosen such that the magnetic field on the die surface is within the specified limits. the typi cal distance ?z? between the magnet and the package surface is 0.5mm to 1.8mm with the recommended magnet (6mm x 2.5mm). larger gap s are possible, as long as the required magnetic field strength stays within the defined limits. a magnetic field outside the specified range may still produce acceptable results, but with reduced accuracy. the out-of-range condition will be indicated, when the agc is at the limits (agc= 0: field too strong; agc=63=(3f h ): field too weak or missing magnet. figure 32. bz field distribution along the x-axis of a 6mm? diametric magnetized magnet figure 32 shows a cross sectional view of the vertical magnetic field co mponent bz between the north and south pole of a 6mm diameter magnet, measured at a vertical distance of 1mm. the poles of the magnet (maximum level) are about 2.8mm from the magnet center, which is almost at the outer magnet edges. the magnetic field reaches a peak amplitude of ~ 106mt at the poles. the hall elements are located at a radius of 1mm (indicated as squares at the bottom of the graph). due to the side view, the t wo hall elements at the y-axis are overlapping at x = 0mm, therefore only 3 hall elements are shown. at 1mm radius, the peak amplitude is ~ 46mt, respectively a differential amplitude of 92mt. the vertical magnetic field b z follows a fairly linear pattern up to about 1.5mm radius. consequently, even if the magnet is not perfectly centered, the differential amplitude will be the same as for a centered magnet. for example, if the magnet is misaligned in x-axis by -0.5 mm, the two x-hall sensors will measure 70mt (@x = -1.5mm) and -22mt (@x = -0.5mm). again, the differential amplitude is 92mt. at larger displacements however, the b z amplitude becomes nonlinear, which results in larger errors that mainly affect the accuracy of the system (see also figure 34 )
www.ams.com/AS5030 revision 2.4 38 - 44 AS5030 datasheet - application information figure 33. vertical magnetic field distribution of a cylindrical 6mm ? diametric magnetized magnet at 1mm gap figure 33 shows the same vertical field component as figure 32 , but in a 3-dimensional view over an area of 4mm from the rotational axis. 8.9.2 lateral displacement of the magnet as shown in the magnet specifications (see page 7) , the recommended horizontal position of the magnet axis with respect to the ic package center is within a circle of 0.25mm radius. this includes the placement tolerance of the ic within the package. figure 34 shows a typical error curve at a medium vertical distance of the magnet around 1.2mm (agc = 24). the x- and y- axis of the graph indicate the lateral displacement of the magnet center with respect to the ic center. at x = y = 0, the magnet is perfectly centered over the ic. the total displacement plotted on the graph is for 1mm in both di rections. the z-axis displays the worst case inl error over a full turn at each given x-and y- displacement. the error includes the quant ization error of 0.7. for example, the accuracy for a centered magnet is between 1.0 ~ 1.5 (spec = 2 over full temperature range). within a r adius of 0.5mm, the accuracy is better than 2.0 (spec = 3 over temperature). 4 3 2 1 0 -1 -2 -3 -4 4 3 2 2 1 0 -1 -2 -3 -125 -100 -75 -50 -25 0 25 50 75 100 125 bz [mt] y-displacement [mm] x-displacement [mm] bz; 6m m m ag n et @ z =1mm a rea o f x-y-misalig nm ent fr om center: +/- 0.5 mm cir cle of ha ll ele ments o n chi p: 1 mm rad i us n s
www.ams.com/AS5030 revision 2.4 39 - 44 AS5030 datasheet - application information figure 34. typical error curve of inl error over lateral displacement (including quantization error) 8.9.3 magnet size figure 32 to figure 34 in this chapter describe a cylindrical magnet with a diameter of 6mm. smaller magnets may also be used, but since the poles are closer together, the linear range will also be smaller and consequently the tolerance for lateral misalignment will a lso be smaller. if the 0.25mm lateral misalignment radius (rotation axis to ic package center) is too tight, a larger magnet can be used. lar ger magnets have a larger linear range and allow more misalignment. however at the same time the slope of the magnet is more flat which results in a lower differential amplitude. this requires either a stronger magnet or a smaller gap between ic and magnet in order to operate in the amplitude-controlled a rea (agc > 0 and agc < 63). in any case, if a magnet other than the recommended 6mm diameter magnet is used, two parameters should be verified: ?? verify that the magnetic field produces a sinusoidal wave, when the magnet is rotated. note that this can be done with the sin- /cos- outputs of the AS5030, e.g. rotate the magnet at constant speed and analyze the sin- (or cos-) output with an fft-analyzer. it is recommended to disable the agc for this test. ?? verify that the b z -curve between the poles is as linear as possible. this curve may be available from the magnet supplier(s). alternatively, the sin- or cos- output of the AS5030 may also be used together with an x-y- table to get a b z -scan of the magnet. furthermore, the sinewave tests described above may be re-run at defined x-and y- misplacements of the magnet to determine the maximum acceptabl e lateral displacement range. it is recommended to disable the agc for both these tests. note: for preferred magnet suppliers, please refer to the ams website (rotary encoder section). -1000 -750 -500 -250 0 250 500 750 1000 -1000 - 750 -500 -250 0 250 500 750 1000 0,000 0,500 1,000 1,500 2,000 2,500 3,000 3,500 4, 000 4,500 5,000 inl [] x displacement [m] y displacem ent [m ] inl vs. displacement: AS5030 for agc24 4,500-5,000 4,000-4,500 3,500-4,000 3,000-3,500 2,500-3,000 2,000-2,500 1,500-2,000 1,000-1,500 0,500-1,000 0,000-0,500
www.ams.com/AS5030 revision 2.4 40 - 44 AS5030 datasheet - application information 8.10 physical placem ent of the magnet the best linearity can be achieved by placing the center of the magnet exactly over the defined center of the chip as shown in the drawing below: figure 35. defined chip center and magnet displacement radius magnet placement. the magnet?s center axis should be aligned within a displacement radius r d of 0.25mm from the defined center of the ic. the magnet may be placed below or above the device. the distance should be chosen such that the magnetic field on the die surfa ce is within the specified limits. the typical distance ?z? between the magnet and the package surface is 0.5mm to 1.5mm, provided the use o f the recommended magnet material and dimensions (6mm x 3mm). larger distances are possible, as long as the required magnetic field s trength stays within the defined limits. however, a magnetic field outside the specified range may still produce usable results, but the out-of-range condition will be indicated by magrngn (pin 1). figure 36. vertical placement of the magnet 1 defined center 2.3975 +/-0.055mm 3.2mm 3.2mm area of recommended maximum magnet misalignment r d 2.3975 +/-0.055mm 0. 77 +/- 0.15mm 0. 23 +/- 0.1mm z s n package surface die surface
www.ams.com/AS5030 revision 2.4 41 - 44 AS5030 datasheet - package drawings and markings 9 package drawings and markings the device is available in a 16-pin tssop package. figure 37. 16-pin tssop package marking: yywwmzz. yy ww m zz last two digits of the year manufacturing week assembly plant identifier assembly traceability code symbol min nom max a- -1.20 a1 0.05 - 0.15 a2 0.80 1.00 1.05 b0.19 - 0.30 c0.09 - 0.20 d 4.90 5.00 5.10 e - 6.40 bsc - e1 4.30 4.40 4.50 e - 0.65 bsc - l 0.45 0.60 0.75 l1 - 1.00 ref - symbol min nom max r0.09 - - r1 0.09 - - s0.20 - - 10o 8o 2 - 12 ref - 3 - 12 ref - aaa - 0.10 - bbb - 0.10 - ccc - 0.05 - ddd - 0.20 - n16 AS5030 yywwmzz notes: 1. dimensioning & tolerancing conform to asme y14.5m-1994 . 2. all dimensions are in millimeters. angles are in degrees.
www.ams.com/AS5030 revision 2.4 42 - 44 AS5030 datasheet - package drawings and markings jedec package outline standard: mo - 153 ab thermal resistance r th(j-a) : 89 k/w in still air, soldered on pcb 9.1 recommended pcb footprint figure 38. pcb footprint recommended footprint data symbol mm inch a7.260.286 b4.930.194 c0.360.014 d0.650.0256 e4.910.193
www.ams.com/AS5030 revision 2.4 43 - 44 AS5030 datasheet - ordering information 10 ordering information the devices are available as the standard products shown in table 7 . note: all products are rohs compliant and ams green. buy our products or get free samples online at www.ams.com/icdirect technical support is available at www.ams.com/technical-support for further information and requests, email us at sales@ams.com (or) find your local distributor at www.ams.com/distributor table 7. ordering information ordering code description delivery form package AS5030-atsu 1 box = 100 tubes 96 devices tubes 16-pin tssop AS5030-atst 1 reel = 4500 devices tape & reel 16-pin tssop
www.ams.com/AS5030 revision 2.4 44 - 44 AS5030 datasheet - copyrights copyrights copyright ? 1997-2013, ams ag, tobelbaderstrasse 30, 8141 unterpremstaetten, austria-europe. trademarks registered ?. all right s reserved. the material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written con sent of the copyright owner. all products and companies mentioned are trademarks or registered trademarks of their respective companies. disclaimer devices sold by ams ag are covered by the warranty and patent indemnification provisions appearing in its term of sale. ams ag makes no warranty, express, statutory, implied, or by description rega rding the information set forth herein or regarding the freedom of the described devices from patent infringement. ams ag reserves the right to change specifications and prices at any time and without notice. therefore, prior to designing this product into a system, it is necessary to check with ams ag for current information. this product is intended for use in normal commercial applications. applications requiring extended temperature range, unusual environmental requirements, or high reliabi lity applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without addi tional processing by ams ag for each application. for shipments of less than 100 parts the manufacturing flow might show deviations from the stan dard production flow, such as test flow or test location. the information furnished here by ams ag is believed to be correct and accurate. however, ams ag shall not be liable to recipien t or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruptio n of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, perfo rmance or use of the technical data herein. no obligation or liability to recipient or any third party shall arise or flow out of ams ag rendering of technical or other services. contact information headquarters ams ag tobelbaderstrasse 30 a-8141 unterpremstaetten, austria tel : +43 (0) 3136 500 0 fax : +43 (0) 3136 525 01 for sales offices, distributors and representatives, please visit: http://www.ams.com/contact

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